The present invention generally relates to a method for fabricating a thin film transistor and more particularly, relates to a method for fabricating a low temperature polysilicon thin film transistor that incorporates a multi-layer channel passivation step.
In recent years, large liquid crystal cells have been used in flat panel displays. The liquid crystal cells are normally constructed by two glass plates joined together with a layer of a liquid crystal material sandwiched in-between. The glass substrates have conductive films coated thereon with at least one of the substrates being transparent. The substrates are connected to a source of power to change the orientation of the liquid crystal material. A possible source of power is a thin film transistor that is used to separately address areas of the liquid crystal cells at very fast rates. The TFT driven liquid crystal cells can be advantageously used in active matrix displays such as for television and computer monitors.
As the requirements for resolution of liquid crystal monitors increase, it becomes desirable to address a large number of separate areas of a liquid crystal cell, called pixels. For instance, in a modern display panel, more than 3,000,000 pixels may be present. At least the same number of transistors must therefore be formed on the glass plates so that each pixel can be separately addressed and left in the switched state while other pixels are addressed.
Thin film transistors are frequently made with either a polysilicon material or an amorphous silicon material. For TFT structures that are made of amorphous silicon material, a common structure is the inverted staggered type which can be back channel etched or tri-layered. The performance of a TFT and its manufacturing yield or throughput depend on the structure of the transistor. For instance, the inverted staggered back channel etched TFT can be fabricated with a minimum number of six masks, whereas other types of inverted staggered TFT require a minimum number of nine masks. The specification for a typical inverted staggered back channel etched TFT includes an amorphous silicon that has a thickness of 3,000 xc3x85, a gate insulator of silicon nitride or silicon oxide, a gate line of Mo/Ta, a signal line of Al/Mo and a storage capacitor. The requirement of a thick amorphous silicon layer in the TFT device is a drawback for achieving a high yield fabrication process since deposition of amorphous silicon is a slow process. A major benefit for the amorphous silicon TFT is its low leakage current which enables a pixel to maintain its voltage. On the other hand, an amorphous silicon TFT has the drawback of a low charge current (or on current) which requires an excessive amount of time for a pixel to be charged to its required voltage.
FIG. 1 shows an enlarged, cross-sectional view of a conventional amorphous silicon TFT structure. Amorphous TFT 10 is built on a low cost glass substrate 12. On top of the glass substrate 12, a gate electrode 14 is first deposited of a refractory metal such as Cr, Al or Al alloy and then formed. A gate insulating layer 16 is normally formed in an oxidation process. For instance, a high density TaOx on a Ta gate can be formed to reduce defects such as pin holes and to improve yield. Another gate insulating layer 20 is then deposited of either silicon oxide or silicon nitride. An intrinsic amorphous silicon layer 22 is then deposited with a n+ doped amorphous silicon layer 24 deposited on top to improve its conductivity. Prior to the deposition of the doped amorphous silicon layer 24, an etch stop 26 is first deposited and formed to avoid damages to the amorphous silicon layer 22 in a subsequent etch process for a contact hole. The doped amorphous silicon layer 24 is formed by first depositing the amorphous silicon layer in a chemical vapor deposition process and then implanting ions in an ion implantation process. Boron ions are normally used to achieve n+ polarity. A drain region 30 and a source region 32 are then deposited and formed with a pixel electrode layer 34 of ITO (indium-tin-oxide) material deposited and formed on top. The drain region 30 and the source region 32 are normally deposited of a conductive metal layer. A suitable conductive metal may be a bilayer of Cr/Al. The structure is then passivated with a passivation layer 36.
A second conventional inverted staggered type TFT 40 is shown in FIG. 2. The TFT 40 is frequently called the back channel etched type inverted staggered TFT. A gate electrode 42 is first formed on a non-conducting glass substrate 38. The gate electrode 42 is connected to a gate line (not shown) laid out in the row direction. A dielectric material layer 44 of either silicon oxide or silicon nitride is used to insulate the gate electrode 42. After an amorphous silicon layer 46 and a contact layer 48 are sequentially deposited, patterned and etched, source electrode 50 and drain electrode 52 are formed to provide a channel 54 in-between the two electrodes, hence the name back channel etched TFT. The source electrode 50 of each TFT is connected to a transparent pixel electrode 56 independently formed in the area surrounded by the gate lines and the drain lines (not shown). A transparent passivation layer 58 of a material such as silicon nitride is deposited on the completed structure.
As shown in FIG. 2, the gate electrode 42 is frequently formed of chromium or other similar metals on the transparent glass substrate 38. The dielectric layer 44 of gate oxide or silicon nitride is formed to insulate the upper surface of the glass substrate 38 including the top surface of the gate electrode 42. A semi-conducting layer 46, which may be formed of amorphous silicon is stacked on the dielectric film 44 over the gate electrode 42. The drain electrode 52 and the source electrode 50 are formed on the semi-conducting film 46 and are separated from each other by a predetermined distance forming the channel section 54. The two electrodes each has a contact layer of 48 and a metal layer which are electrically connected to the semi-conducting layer 46. The transparent electrode 44 may be formed of ITO.
A second type of TFT is made by using a polysilicon material. Polysilicon is more frequently used for displays that are designed in a smaller size, for instance, up to three inch diagonal for a projection device. At such a small size, it is economical to fabricate the display device on a quartz substrate. Unfortunately, large area display devices cannot be made on quartz substrates. The desirable high performance of polysilicon can be realized only if a low temperature process can be developed to enable the use of non-quartz substrates. For instance, in a recently developed process, large area polysilicon TFT can be manufactured at processing temperatures of less than 600xc2x0 C. In the process, self-aligned transistors are made by depositing polysilicon and gate oxide followed by source/drain regions which are self-aligned to the gate electrode. The device is then completed with a thick oxide layer, an ITO layer and aluminum contacts.
Polysilicon TFTs have the advantage of a high charge current (or on current) and the drawback of a high leakage current. It is difficult to maintain the voltage in a pixel until the next charge in a polysilicon TFT due to its high leakage current. Polysilicon also allows the formation of CMOS devices, which cannot be formed by amorphous silicon. For the fabrication of larger displays, a higher mobility may be achieved by reducing the trap density around the grain boundaries in a hydrogenation process.
When compared to the amorphous silicon thin film transistors, the low temperature polysilicon TFTs have higher mobility and higher drive current. However, due to the fabrication technology and the structure of the polysilicon element, the activation process (or the annealing process) for the dopant ions in the source area and the drain area has become an important issue. For instance, FIG. 3 illustrates a conventional method for an activation process for a polysilicon island 60. The polysilicon island 60 is constructed by a polysilicon layer 62 with a photoresist layer 64 patterned on top to cover a channel section 66 of the polysilicon island 62. However, in this conventional method for activating the dopant ions, i.e. N+ dopant ions by either laser irradiation or by rapid thermal annealing (RTA), several process disadvantages have been encountered. For instance, a direct contact of the photoresist layer 64 with the polysilicon layer 62 causes contamination to the polysilicon by residual photoresist material left behind after a photoresist removal process. Moreover, other processing difficulties such as dopant out-diffusion and dopant lateral diffusion have been encountered. The conventional method for dopant activation, therefore, must be improved before it can be used to produce high quality thin film transistors.
It is therefore an object of the present invention to provide a method for fabricating a low temperature polysilicon thin film transistor that does not have the drawbacks or the shortcomings of the conventional method.
It is another object of the present invention to provide a method for fabricating a low temperature polysilicon thin film transistor that incorporates multi-layer channel passivation step.
It is a further object of the present invention to provide a method for fabricating a low temperature polysilicon thin film transistor in which dopant ions are activated by laser irradiation without causing damages to a channel region.
It is another further object of the present invention to provide a method for activating dopant ions in a polysilicon gate in a thin film transistor by depositing a multi-layer passivation layer on top of a channel region of a polysilicon gate prior to a laser activation step.
It is still another object of the present invention to provide a method for activating dopant ions in a polysilicon gate in a TFT by first depositing a first insulating material layer, a metal layer and a second insulating material layer on top of a polysilicon gate to shield a channel region during a laser activation process.
It is yet another object of the present invention to provide a method for activating dopant ions in a polysilicon gate in a TFT structure wherein dopant ions in both a NMOS and a PMOS are activated simultaneously in the same step.
In accordance with the present invention, a method for fabricating a low temperature polysilicon thin film transistor that incorporates a multi-layer channel passivation step is provided.
In a preferred embodiment, a method for activating dopant ions in a polysilicon gate in a thin film transistor utilizing multi-layer channel passivation can be carried out by the operating steps of first providing a substrate; forming a polysilicon island on the substrate; depositing a first insulating material layer overlying the polysilicon island; depositing a metal layer overlying the first insulating material layer; depositing a second insulating material layer overlying the metal layer; depositing a photoresist layer on top of the second insulating material layer and patterning the photoresist layer to overlie only a channel region in the polysilicon island; etching away the first insulating material layer, the metal layer, and the second insulating material layer except an area covered by the patterned photoresist layer; removing the patterned photoresist layer; doping by implantation N+ and Nxe2x88x92 dopant ions into the polysilicon island except an area covered by the first and second insulating material layers and the metal layer; activating the N+ and Nxe2x88x92 dopant ions in the polysilicon island by laser irradiation through the first and second insulating material layers and the metal layer situated on top; and removing the second insulating material layer.
The method for activating dopant ions in a polysilicon gate in a TFT structure utilizing multi-layer channel passivation may further include the step of depositing the second insulating material layer of a material selected from the group consisting of SiO2, Si3N4 and SiON. The method may further include the step of depositing the first and second insulating material layers by a method of plasma enhanced CVD or spin-on coating. The method may further include the step of depositing the first and second insulating material layers to a thickness between about 100 xc3x85 and about 2000 xc3x85, and preferably between about 500 xc3x85 and about 1500 xc3x85. The method may further include the step of activating the N+ and Nxe2x88x92 dopant ions by scanning the polysilicon island with an excimer laser. The method may further include the step of forming the first insulating material layer of SiO2. The method may further include the step of forming the first insulting material layer to a thickness between about 500 xc3x85 and about 1500 xc3x85. The method may further include the step of depositing the metal layer of a material selected from the group consisting of Mo, MoW, AlNd and Ta.
The present invention is further directed to a method for fabricating a low temperature polysilicon TFT which can be carried out by the operating steps of first providing a substrate; forming a polysilicon island on the substrate; depositing a first insulating material layer, a metal layer and a second insulating material layer sequentially overlying the polysilicon island; depositing a first photoresist layer on top of the second insulating material layer without contacting the polysilicon island and patterning the photoresist layer to overlie only a channel region in the polysilicon island; etching away the first insulating material layer, the metal layer and the second insulating material layer except an area covered by the patterned first photoresist layer; removing the patterned first photoresist layer; doping by implantation N+ and Nxe2x88x92 dopant ions into the polysilicon island except the area covered by the patterned first photoresist layer; activating the N+ and Nxe2x88x92 dopant ions in the polysilicon island by laser irradiation through the remaining first and second insulating material layers and the metal layer situated on top; and removing the remaining second insulating material layer from the polysilicon island.
The method for fabricating a low temperature polysilicon TFT may further include the step of depositing the metal layer to a thickness between about 2000 xc3x85 and about 4000 xc3x85. The method may further include the step of depositing the first and the second insulating material layers of a material selected from the group consisting of SiO2, Si3N4 and SiON. The method may further include the step of depositing the first and second insulating material layers by a technique of PECVD or spin-on coating. The method may further include the step of depositing the first and the second insulating material layers to a thickness between about 100 xc3x85 and about 1500 xc3x85.
The present invention is still further directed to a method for forming a polysilicon gate in a TFT structure incorporating multi-layer channel passivation step which can be carried out by the operating steps of forming a polysilicon island on a substrate; depositing a multi-layer passivation layer including a first insulating material layer on the bottom, a metal layer in the middle and a second insulating material layer on top overlying the polysilicon island; patterning a photoresist layer on the multi-layer passivation layer and forming the multi-layer passivation layer to overlap only a channel region in the polysilicon gate; implanting N+ and Nxe2x88x92 dopant ions into the polysilicon gate except the channel region; irradiating the polysilicon island through the multi-layer passivation layer with laser energy to activate the N+ and Nxe2x88x92 dopant ions; and removing the second insulating material layer from the polysilicon island.
The method for forming a polysilicon gate in a TFT structure that incorporates a multi-layer channel passivation step may further include the step of forming the first and second insulating material layers from a material selected from the group consisting of SiO2, Si3N4 and SiON. The method may further include the step of depositing the multi-layer passivation layer to a total thickness between about 3000 xc3x85 and about 7000 xc3x85. The method may further include the step of depositing the first and second insulating material layers by a plasma enhanced CVD technique or by a spin-on coating technique.